The present invention relates to interconnect systems, and more particularly to systems using programmable interconnect chips to establish electrical connections in circuit boards.
Over the last several years circuit-board-level system complexity has dramatically increased due to advances in the integrated circuit and discreet component technology. Such advances provide products with improved functionality, performance, integration and cost. However, they also make the system verification so complex as to become a significant bottle-neck in the development process.
To facilitate the board-level system verification, programmable interconnect systems have been proposed that use programmable interconnect chips to quickly and cheaply replicate the board functionality. The programmable interconnect chips are connected to other components of the board ("user components") and are programmed to provide the desired connections between the user components.
One such programmable interconnect system is disclosed in the U.S. patent application Ser. No. 07/410,194 filed Sep. 20, 1989 by Mohsen, now U.S. Pat. No. 5,377,124 set to issue on Dec. 27, 1994. In that system, every interconnect chip is connected to every other interconnect chip to provide a flexible interconnect architecture.
Another example of a programmable interconnect system is a channel-routing interconnect system disclosed in the U.S. Pat. No. 5,036,473 issued Jul. 30, 1991 to Butts et al. In that system, each user component chip is surrounded by, and connected to, interconnect chips. Another example is a partial crossbar interconnect system disclosed in the same patent. The partial crossbar system requires fewer interconnect chips but it generally does not allow connecting any pin of a user component to any other pin of a user component. For example, in the system of FIG. 7 of the Butts et al. patent, pin C of logic chip 1 can be connected only to pins C and D of logic chip 4 but not to pins A, B, E, F, G, H of chip 4.
It is desirable to provide an interconnect system which would allow connecting any pin of a user component to any other pin of a user component and which would provide a large number of low-delay conductive paths between user components.